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The mainstream adoption of 3D-IC has change into a query mark because of vital challenges starting from early-stage chip designs to 3D meeting exploration to remaining design signoff. A brand new EDA instrument claims to deal with these points by integrating thermal evaluation straight into all levels of the IC design circulate, spanning early evaluation to signoff evaluation, whereas providing multiple-use fashions.
At this 12 months’s Design Automation Convention (DAC) in San Francisco, California, Siemens EDA unveiled Calibre 3DThermal software program for thermal evaluation, verification, and debugging in 3D built-in circuits (3D-ICs). It permits chip designers to quickly mannequin, visualize, and mitigate thermal results of their designs from early-stage chip design to package-inward exploration to design signoff.
Determine 1 Calibre 3DThermal is a thermal evaluation answer based mostly on a whole understanding of the 3D-IC meeting. Supply: Siemens EDA
In all design flows, Calibre 3DThermal captures and analyzes thermal knowledge throughout the whole design lifecycle. Siemens EDA has already joined forces with UMC to deploy a thermal evaluation circulate based mostly on Calibre 3DThermal.
What’s hampering 3D ICs
Semiconductor engineering groups specializing in designing and manufacturing bleeding edge, next-generation chips are turning to chiplets and 3D-IC architectures to combine extra performance into ever-shrinking footprints. Nevertheless, regardless of a number of speak, commercially obtainable semiconductors based mostly on 3D-IC architectures are nonetheless fairly laborious to search out within the market.
Why? 3DIC architectures—which place a number of dies or chiplets subsequent to at least one one other and even stack dies vertically in a single bundle—current a variety of latest complexities and challenges because of increased numbers of lively dies in shut proximity to one another or stacked vertically.
In different phrases, squeezing a number of lively dies in such shut proximity—side-by-side or stacked vertically—in a single bundle comes with a bunch of latest and vexing challenges. These challenges—generally categorized as multi-physics—typically relate to controlling warmth dissipation since extreme warmth can impression the tip system’s efficiency and reliability.
“There was a view that 3D IC goes to take over the world, however nobody goes to desert Moore’s Legislation transistor scaling,” mentioned Michael White, senior director of bodily verification product administration for Calibre design options at Siemens EDA. “Nevertheless, 3D IC will likely be used for heterogeneous options in compute-intensive synthetic intelligence (AI) chips.”
At superior nodes like 2-nm, 3D IC is smart, he added. “Whether or not it’s software processor, CPU or GPU, components like I/O and HBM are going to be separate dies or separate chiplets, and it’s all going to be packaged in 2.5D or 3D IC.” Nevertheless, in these superior packages, controlling warmth dissipation turns into crucial.
Furthermore, design engineers can’t afford to attend till the meeting is full to determine and proper errors; it will possibly severely disrupt design schedules.
“There may be quite a lot of warmth to be managed,” White mentioned. “In any other case, it will possibly impression transistor habits on this new multi-physics area.” He additionally added that thermal impacts might couple with stress impacts coming from new supplies, how we stack, and putting of by way of silicon vias (TSVs) near lively transistors.
Thermal evaluation to rescue
White makes the case for a shift-left strategy with Calibre bodily verification to assist designers do issues proper the primary time as an alternative of near tape-out. Whereas speaking to EDN earlier than the launch of Calibre3DThermal, he pointed to its key characteristic, feasibility evaluation, which permits chip designers to begin the preliminary evaluation with minimal inputs. “As soon as extra info is offered, it constantly refines the accuracy of the evaluation.”
Determine 2 The shift-left strategy permits chip designers to determine and resolve points early in design circulate with signoff-quality options. Supply: Siemens EDA
John Ferguson, senior director of DRC/3DIC product administration for Calibre design options, identified that chip designers spend years growing complicated 3D ICs, and after a thermal signoff, in the event that they discover an issue, there may be nothing they will do about it. “The thought of feasibility evaluation is to begin discovering potential issues early.”
Chip designers can later carry out extra detailed analyses contemplating metalization particulars and their impression on thermal issues as extra detailed info turns into obtainable. This progressive strategy permits designers to refine their evaluation, apply fixes like floorplanning modifications, and add stacked vias or TSVs to keep away from thermal hotspots and dissipate warmth extra successfully.
The iterative course of continues till the ultimate meeting is full. Ferguson is fast to notice that Calibre3DThermal is a bit completely different than conventional thermal evaluation. “We have now a sooner manner of performing thermal evaluation during which the Calibre half will work upfront to take a look at the die stage info, create correct fashions, and move that for creating fashions on the bundle stage.”
Calibre with multi-use fashions
Calibre 3DThermal—developed to deal with the challenges of 3D-IC architectures the place controlling warmth dissipation is a key requirement—gives quick and correct approaches to figuring out and quickly addressing complicated thermal points. It permits designers to iterate thermal evaluation at whichever design stage they’re engaged on.
Thermal evaluation at this superior stage requires a whole understanding of the 3D-IC meeting, so Calibre 3DThermal embeds a customized model of Siemens’ Simcenter Flotherm software program solver engine to create exact chiplet-level thermal fashions for static or dynamic simulation of full 3D-IC assemblies. Subsequent, debugging is streamlined by way of the standard Calibre RVE software program outcomes viewer.
It’s price noting that even if you put a identified good die (KGD) right into a bundle, you would possibly get warmth points.
“After getting extra dies, you’ll be able to carry out extra mature thermal evaluation at a way more fine-grained stage,” Ferguson mentioned. “Once you deliver all dies into the bundle, that’s if you add further accuracy after which have a look at selective chiplets or selective IPs in these chiplets.”
Now that chip designers have info on the dies and bundle ranges, this info could be handed upstream to the board stage and even to the massive system stage, like a jet engine design.
Associated Content material
A thermal-aware IC design methodology
The Significance of 3D IC Ecosystem Collaboration
Reliability challenges in 3D IC semiconductor design
How the Worlds of Chiplets and Packaging Intertwine
Heterogeneous Integration and the Evolution of IC Packaging
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The publish Thermal evaluation instrument goals to reinvigorate 3D-IC design appeared first on EDN.
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